Overview Signal/Power Integrity Checking Service

Major Advantages

Have improved confidence in your design
Independant expert advice
Low cost service
Highlight any potential problems and give suggested improvements
No need to own expensive SI/PI tools
More detailed SI/PI simulation can be performed (additional cost)

Introduction

With the Signal/Power Integrity Checking Service our aim is not to run full SI/PI analysis on your design, but rather run a relatively quick health check on the PCB board design to determine if there are areas of concern in the design. Reports report will be generated that give the following details: -

Trace reference Checking
Trace reference-aware impedance
Trace reference-aware coupling (crosstalk)
Differential pair routing phase
Number of vias
Supply Voltage Drop
Power Plane/ Power Trace Current Density
Power Via Current and Current Density

Based on the simulation results we will make recommendations for improvements in the PCB layout and also if we believe that more in-depth simulations are required. Note that as we are not using IBIS or SPICE models of the drivers and receivers for these simulations as our aim is to give a fast turnaround service that carries out basic checks on a PCB design for impedance, crosstalk, DC Drop and current, current density and the like.

Electrical Rules and DC Power Delivery Checking

As silicon geometries continue to shrink edge rates reduce and the demands for impedance and crosstalk control increase. Although many PCB layout tools include Design Rule Checks (DRC) these are often based purely on dimensional data (width, spacing, height) and do not adequately validate the electrical characteristics of the interconnect. As an example, DRC checks often do not validate the effect of signals crossing plane splits or changes in reference planes causing impedance discontinuities.

In addition there has been a proliferation of supply voltages which mean that the available space for each of the power delivery networks is compromised. As Engineers struggle to fit the required functionality in small form factors the power planes become increasingly peppered with via holes that compromise both the AC and DC performance of the PDN.

Electrical Rules Check Example

Here is an example of a PCB design where the nets have been grouped. In this case not all of the nets are included in the check, but all the major interfaces in the design have been covered.

It is possible to setup the typical rise time and voltage swing for each type of signal, and this is used to determine the amount of crosstalk. Once the simulation has been completed a range of reports are generated are "live" when in the tools, that is, as we review the results it is possible to click on a line in the report and this will open the design so that it is possible to investigate the underlying cause of any issues observed.
Examples of some of the available reports and graphical overlays available from within the tool are shown below.

DC Power Delivery

Setup of the design is a little more complex in the case of DC power delivery checking. Most PCB tools do not allow you to state the plating thickness in the via barrels, although you can often create the layer stack with the correct copper weights and plating. From within Cadence Allegro layout tools it is possible to specify the plating for the vias before entering the PowerDC tool.

For each power supply that needs to be simulated it is necessary to set source typically this is placed at the DC-DC/VRMs, but may also be at a connector or other circuit element. When specifying the DC source it is possible include the output voltage tolerance and any connection resistance. For board mounted DC-DC converters with external regulation voltage sense, connection resistance can typically be ignored.

Setup details for the loads can be a little more complex depending on the amount of detail that is known about the devices used on the board. For example in most PCB designs the designer will know the total current consumption of a device, but not how the current is distributed amongst the balls/pins of the device. In this case the designer would need to simply distribute the total current consumption across the available power/gnd connections.

However for a company that is designing both the IC/package and PCB this additional information may be available and therefore the current can be mapped across the available connections in a more accurate manner. In addition it is possible to make the connections an equipotential at the load connections, you might use this if the load device supported a voltage remote sense at the die.

In addition it may be necessary to specify component characteristics for series elements (such as resistors, inductors or ferrite beads). Note that these need only be simple resistive models as we are only determining the DC performance of the PDN system.
Constraints for maximum voltage drop at the loads are automatically assigned when the sink current is assigned, but it also

Via Current (both global and individual)
Via current density
Plane Current density
Trace Current density
Discrete Currents

Once the simulation completes both textual and graphical reports are available, some example output is shown below. From the output of the PowerDC report we will interpret the results and provide guidance whether and how the design should be improved to minimise issues with current density and voltage drop.